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TDA2SA Datasheet(PDF) 148 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 148 Page - Texas Instruments |
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148 / 427 page  148 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Specifications Copyright © 2015–2019, Texas Instruments Incorporated Table 5-9. Maximum Supported Frequency (continued) Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name GPU GPU_FCLK1 Func GPU_CLK GPU_CORE_GCLK CORE_GPU_CLK DPLL_CORE PER_GPU_CLK DPLL_PER GPU_GCLK DPLL_GPU GPU_FCLK2 Func GPU_CLK GPU_HYD_GCLK CORE_GPU_CLK DPLL_CORE PER_GPU_CLK DPLL_PER GPU_GCLK DPLL_GPU GPU_ICLK Int 266 GPU_L3_GICLK CORE_X2_CLK DPLL_CORE HDMI PHY DSS_HDMI_PHY_ CLK Func 38.4 HDMI_PHY_GFCLK FUNC_192M_CLK DPLL_PER I2C1 I2C1_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE I2C1_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER I2C2 I2C2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE I2C2_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER I2C3 I2C3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE I2C3_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER I2C4 I2C4_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE I2C4_FCLK Func 96 PER_96M_GFCLK FUNC_192M_CLK DPLL_PER I2C5 I2C5_ICLK Int 266 IPU_L3_GICLK CORE_X2_CLK DPLL_CORE I2C5_FCLK Func 96 IPU_96M_GFCLK FUNC_192M_CLK DPLL_PER IEEE1500_2_OCP PI_L3CLK Int & Func 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE IPU1 IPU1_GFCLK Int & Func 425.6 IPU1_GFCLK DPLL_ABE_X2_CL K DPLL_ABE CORE_IPU_ISS_B OOST_CLK DPLL_CORE IPU2 IPU2_GFCLK Int & Func 425.6 IPU2_GFCLK CORE_IPU_ISS_B OOST_CLK DPLL_CORE IVA IVA_GCLK Int IVA_GCLK IVA_GCLK IVA_GFCLK DPLL_IVA L3_INSTR L3_CLK Int L3_CLK L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE L3_MAIN L3_CLK1 Int L3_CLK L3MAIN1_L3_GICLK CORE_X2_CLK DPLL_CORE L3_CLK2 Int L3_CLK L3INSTR_L3_GICLK CORE_X2_CLK DPLL_CORE L4_CFG L4_CFG_CLK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE L4_PER1 L4_PER1_CLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE L4_PER2 L4_PER2_CLK Int 133 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE L4_PER3 L4_PER3_CLK Int 133 L4PER3_L3_GICLK CORE_X2_CLK DPLL_CORE L4_WKUP L4_WKUP_CLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE MAILBOX1 MAILBOX1_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX2 MAILBOX2_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX3 MAILBOX3_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX4 MAILBOX4_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX5 MAILBOX5_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX6 MAILBOX6_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX7 MAILBOX7_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX8 MAILBOX8_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE MAILBOX9 MAILBOX9_FLCK Int 266 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE |
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