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TDA2SA Datasheet(PDF) 144 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 144 Page - Texas Instruments |
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144 / 427 page  144 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Specifications Copyright © 2015–2019, Texas Instruments Incorporated Table 5-8. Supported OPP vs Max Frequency(2) (continued) DESCRIPTION OPP_NOM OPP_OD OPP_HIGH MAX FREQ. (MHz) MAX FREQ. (MHz) MAX FREQ. (MHz) VD_CORE CORE_IPUx_CLK 212.8 N/A N/A L3_CLK 266 N/A N/A DDR2 400 (DDR2-800) N/A N/A DDR3 / DDR3L 532 (DDR3-1066) N/A N/A VD_RTC RTC_FCLK 0.034 N/A N/A (1) N/A in this table stands for Not Applicable (2) Maximum supported frequency is limited according to , Speed Grade Maximum Frequency). 5.5.3 Maximum Supported Frequency Device modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM. Table 5-9 lists the clock source options for each module on this device, along with the maximum frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table. Table 5-9. Maximum Supported Frequency Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name AES1 AES1_L3_CLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE AES2 AES2_L3_CLK Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE COUNTER_32K COUNTER_32K_F CLK Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC1 COUNTER_32K_IC LK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE CTRL_MODULE_B ANDGAP L3INSTR_TS_GCL K Int 4.8 L3INSTR_TS_GCLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE CTRL_MODULE_C ORE L4CFG_L4_GICLK Int 133 L4CFG_L4_GICLK CORE_X2_CLK DPLL_CORE CTRL_MODULE_ WKUP WKUPAON_GICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE DCAN1 DCAN1_FCLK Func 38.4 DCAN1_SYS_CLK SYS_CLK1 OSC1 SYS_CLK2 OSC2 DCAN1_ICLK Int 266 WKUPAON_GICLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE DCAN2 DCAN2_FCLK Func 38.4 DCAN2_SYS_CLK SYS_CLK1 OSC1 DCAN2_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE DES3DES DES_CLK_L3 Int 266 L4SEC_L3_GICLK CORE_X2_CLK DPLL_CORE DLL EMIF_DLL_FCLK Func EMIF_DLL_FC LK EMIF_DLL_GCLK EMIF_DLL_GCLK DPLL_DDR DLL_AGING FCLK Int 38.4 L3INSTR_DLL_AGING _GCLK SYS_CLK1 OSC1 DPLL_ABE_X2_CL K DPLL_ABE |
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