TDA2SA datasheet(270/427 Pages) TI2

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B0 B1

A30 A31

B30 B31 C0

C1 C2

C31

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data Out/Transmit)

ACLKR/X (CLKRP = CLKXP = 0)(B)

ACLKR/X (CLKRP = CLKXP = 1)(A)

270

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Timing Requirements and Switching Characteristics

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

Figure 7-35. McASP Output Timing

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and

DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Control

Module Chapter.

Table 7-51 through Table 7-58 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see

Figure 7-36 through Figure 7-43).

TDA2SA Datasheet(PDF) 270 Page - Texas Instruments