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TDA2SA Datasheet(PDF) 304 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 304 Page - Texas Instruments |
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304 / 427 page  mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR1041 SDR1042L SDR1042H SDR1045 SDR1046 SDR1045 SDR1046 MMC1_12 mmc1_clk mmc1_cmd mmc1_dat[3:0] SDR1044 SDR1048 SDR1043 SDR1047 SDR1041 SDR1042H SDR1042L MMC1_11 304 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-99. Switching Characteristics for MMC1 - SD Card SDR104 Mode (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR1042 H tw(clkH) Pulse duration, mmc1_clk high 0.5*P- 0.185 (1) ns SDR1042 L tw(clkL) Pulse duration, mmc1_clk low 0.5*P- 0.185 (1) ns SDR1045 td(clkL-cmdV) Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -1.09 0.49 ns SDR1046 td(clkL-dV) Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -1.09 0.49 ns (1) P = output mmc1_clk period in ns Figure 7-64. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode Figure 7-65. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode 7.22.1.7 UHS-I DDR50, 4-bit data Table 7-100 and Table 7-101 present Timing requirements and Switching characteristics for MMC1 - DDR50 in receiver and transmitter mode (see Figure 7-66 and Figure 7-67). Table 7-100. Timing Requirements for MMC1 - SD Card DDR50 Mode NO. PARAME TER DESCRIPTION MODE MIN MAX UNIT DDR50 5 tsu(cmdV-clk) Setup time, mmc1_cmd valid before mmc1_clk transition 1.79 ns DDR50 6 th(clk-cmdV) Hold time, mmc1_cmd valid after mmc1_clk transition 1.6 ns DDR50 7 tsu(dV-clk) Setup time, mmc1_dat[3:0] valid before mmc1_clk transition Pad Loopback 1.79 ns Internal Loopback 1.79 ns DDR50 8 th(clk-dV) Hold time, mmc1_dat[3:0] valid after mmc1_clk transition Pad Loopback 1.6 ns Internal Loopback 1.6 ns |
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