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TDA2SA Datasheet(PDF) 305 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 305 Page - Texas Instruments |
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305 / 427 page ![]() mmc _clk 1 mmc _cmd 1 mmc _dat[3:0] 1 DDR500 DDR501 DDR502 DDR503(max) DDR503(min) DDR504(max) DDR504(min) DDR504(min) DDR504(max) MMC1_14 mmc _clk 1 mmc _cmd 1 mmc _dat[3:0] 1 DDR500 DDR501 DDR502 DDR505 DDR506 DDR508 DDR507 DDR507 DDR508 MMC1_13 305 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-101. Switching Characteristics for MMC1 - SD Card DDR50 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT DDR500 fop(clk) Operating frequency, mmc1_clk 48 MHz DDR501 tw(clkH) Pulse duration, mmc1_clk high 0.5*P- 0.185 (1) ns DDR502 tw(clkL) Pulse duration, mmc1_clk low 0.5*P- 0.185 (1) ns DDR503 td(clk-cmdV) Delay time, mmc1_clk transition to mmc1_cmd transition 1.225 6.6 ns DDR504 td(clk-dV) Delay time, mmc1_clk transition to mmc1_dat[3:0] transition 1.225 6.6 ns (1) P = output mmc1_clk period in ns Figure 7-66. SDMMC - High Speed SD - DDR - Data/Command Receive Figure 7-67. SDMMC - High Speed SD - DDR - Data/Command Transmit NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 4-3 and described in Device TRM, Control Module Chapter. Virtual IO Timings Modes must be used to ensure some IO timings for MMC1. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-102 Virtual Functions Mapping for MMC1 for a definition of the Virtual modes. Table 7-102 presents the values for DELAYMODE bitfield. |
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