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TDA2SA Datasheet(PDF) 309 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 309 Page - Texas Instruments |
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309 / 427 page  SSDR2 mmc2_clk mmc2_cmd mmc2_dat[7:0] SSDR1 SSDR2 SSDR3 SSDR4 MMC2_02 mmc2_clk mmc2_cmd mmc2_dat[7:0] SSDR2 SSDR2 SSDR1 SSDR6 SSDR5 SSDR8 SSDR7 MMC2_01 309 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-105. Switching Characteristics for MMC2 - JC64 Standard SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT SSDR1 fop(clk) Operating frequency, mmc2_clk 24 MHz SSDR2H tw(clkH) Pulse duration, mmc2_clk high 0.5*P- 0.172 (1) ns SSDR2L tw(clkL) Pulse duration, mmc2_clk low 0.5*P- 0.172 (1) ns SSDR3 td(clkL-cmdV) Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -16.96 16.96 ns SSDR4 td(clkL-dV) Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -16.96 16.96 ns (1) P = output mmc2_clk period in ns Figure 7-68. MMC/SD/SDIO in - Standard JC64 - Receiver Mode Figure 7-69. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode 7.22.2.2 High-speed JC64 SDR, 8-bit data, half cycle Table 7-106 and Table 7-107 present Timing requirements and Switching characteristics for MMC2 - High speed SDR in receiver and transmitter mode (see Figure 7-70 and Figure 7-71). Table 7-106. Timing Requirements for MMC2 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT JC643 tsu(cmdV-clkH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.6 ns JC644 th(clkH-cmdV) Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 2.6 ns JC647 tsu(dV-clkH) Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge 5.6 ns JC648 th(clkH-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge 2.6 ns |
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