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TDA2SA Datasheet(PDF) 310 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 310 Page - Texas Instruments |
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310 / 427 page  mmc _clk 2 mmc _cmd 2 mmc _dat 2 [3:0] JC645 JC645 JC646 JC646 JC641 JC642H JC642L MMC2_04 mmc _clk 2 mmc _cmd 2 mmc _dat 2 [3:0] JC644 JC648 JC643 JC647 JC641 JC642H JC642L MMC2_03 310 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-107. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT JC641 fop(clk) Operating frequency, mmc2_clk 48 MHz JC642H tw(clkH) Pulse duration, mmc2_clk high 0.5*P- 0.172 (1) ns JC642L tw(clkL) Pulse duration, mmc2_clk low 0.5*P- 0.172 (1) ns JC645 td(clkL-cmdV) Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -6.64 6.64 ns JC646 td(clkL-dV) Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -6.64 6.64 ns (1) P = output mmc2_clk period in ns Figure 7-70. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode Figure 7-71. MMC/SD/SDIO in - High Speed JC64 - Transmitter Mode 7.22.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle Table 7-108 presents Timing requirements and Switching characteristics for MMC2 - HS200 in receiver and transmitter mode (see Figure 7-72). Table 7-108. Switching Characteristics for MMC2 - JEDS84 HS200 Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT HS2001 fop(clk) Operating frequency, mmc2_clk 192 MHz HS2002H tw(clkH) Pulse duration, mmc2_clk high 0.5*P- 0.172 (1) ns HS2002L tw(clkL) Pulse duration, mmc2_clk low 0.5*P- 0.172 (1) ns HS2005 td(clkL-cmdV) Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -1.136 0.536 ns HS2006 td(clkL-dV) Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -1.136 0.536 ns |
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