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TDA2SA Datasheet(PDF) 312 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 312 Page - Texas Instruments |
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312 / 427 page  mmc _clk 2 mmc _cmd 2 mmc _dat 2 [7:0] DDR1 DDR2 DDR2 DDR5 DDR5 DDR6 DDR6 DDR6 DDR6 DDR5 DDR5 DDR6 DDR6 MMC2_08 mmc _clk 2 mmc _cmd 2 mmc _dat 2 [3:0] DDR1 DDR2H DDR2L DDR3 DDR4 DDR7 DDR8 DDR7 DDR8 DDR7 DDR8 DDR7 MMC2_07 312 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-111. Timing Requirements for MMC2 - JC64 High Speed DDR Mode During Boot (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR7 tsu(dV-clk) Setup time, mmc2_dat[7:0] valid before mmc2_clk transition Boot (1.8V) 1.8 ns Boot (3.3V) 1.8 ns DDR8 th(clk-dV) Hold time, mmc2_dat[7:0] valid after mmc2_clk transition Boot (1.8V) 1.8 (1) ns Boot (3.3V) 1.8 (1) ns (1) This Hold time requirement is larger than the Hold time provided by a typical eMMC component. Therefore, the trace length between the Device and eMMC component must be sufficiently long enough to ensure that the Hold time is met at the Device. Table 7-112. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode During Boot NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT DDR1 fop(clk) Operating frequency, mmc2_clk 48 MHz DDR2H tw(clkH) Pulse duration, mmc2_clk high 0.5*P- 0.172 (1) ns DDR2L tw(clkL) Pulse duration, mmc2_clk low 0.5*P- 0.172 (1) ns DDR5 td(clk-cmdV) Delay time, mmc2_clk transition to mmc2_cmd transition Boot (1.8V) 2.9 7.14 ns Boot (3.3V) 2.9 7.14 ns DDR6 td(clk-dV) Delay time, mmc2_clk transition to mmc2_dat[7:0] transition Boot (1.8V) 2.9 7.14 ns Boot (3.3V) 2.9 7.14 ns (1) P = output mmc2_clk period in ns Figure 7-73. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode Figure 7-74. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode |
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