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TDA2SA Datasheet(PDF) 327 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 327 Page - Texas Instruments |
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327 / 427 page  TRACECLK TRACECTL TRACEDATA[X:0] TPIU4 TPIU4 TPIU2 TPIU1 TPIU3 TPIU5 TPIU5 TPIU_01 5 6 8 7 TCK RTCK JTAG_02 327 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Figure 7-86. JTAG With RTCK Timing 7.25.2 Trace Port Interface Unit (TPIU) CAUTION The I/O timings provided in this section are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 7-139. 7.25.2.1 TPIU PLL DDR Mode Table 7-138 and Figure 7-87 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 7-138. Switching Characteristics for TPIU NO. PARAMETER DESCRIPTION MIN MAX UNIT TPIU1 tc(clk) Cycle time, TRACECLK period 5.56 ns TPIU4 td(clk-ctlV) Skew time, TRACECLK transition to TRACECTL transition -0.96 0.96 ns TPIU5 td(clk-dataV) Skew time, TRACECLK transition to TRACEDATA[17:0] -0.96 0.96 ns Figure 7-87. TPIU—PLL DDR Transmit Mode(1) (1) In d[X:0], X is equal to 15 or 17. In Table 7-139 are presented the specific groupings of signals (IOSET) for use with TPIU signals. Table 7-139. TPIU IOSETs SIGNALS IOSET1 IOSET2 BALL MUX BALL MUX emu0 G21 0 G21 0 emu1 D24 0 D24 0 emu2 F10 2 F10 2 |
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