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TDA2SA Datasheet(PDF) 325 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 325 Page - Texas Instruments |
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325 / 427 page  325 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated NOTE For more information, see the General-Purpose Interface chapter of the Device TRM. NOTE The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi. 7.24 System and Miscellaneous interfaces The Device includes the following System and Miscellaneous interfaces: • Sysboot Interface • Enhanced DMA Interface • Interrupt Controllers (INTC) Interface • Observability Signal (OBS) Interface 7.25 Test Interfaces The Device includes the following Test interfaces: • IEEE 1149.1 Standard-Test-Access Port (JTAG) • Trace Port Interface Unit (TPIU) • Advanced Event Triggering Interface (AET) 7.25.1 IEEE 1149.1 Standard-Test-Access Port (JTAG) The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture) interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to ensure that trstn is always asserted upon power up and the device's internal emulation logic is always properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some third-party JTAG controllers may not drive trstn high but expect the use of a Pullup resistor on trstn. When using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive trstn high before attempting any emulation or boundary-scan operations. The main JTAG features include: • 32KB embedded trace buffer (ETB™) • 5-pin system trace interface for debug • Supports Advanced Event Triggering (AET) • All processors can be emulated via JTAG ports • All functions on EMU pins of the device: – EMU[1:0] - cross-triggering, boot mode (WIR), STM trace – EMU[4:2] - STM trace only (single direction) 7.25.1.1 JTAG Electrical Data/Timing Table 7-134, Table 7-135 and Figure 7-85 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 7-134. Timing Requirements for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 62.29 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 24.92 ns 1b tw(TCKL) Pulse duration, TCK low (40% of tc) 24.92 ns |
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