 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TDA2SA Datasheet(PDF) 322 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TDA2SA Datasheet(HTML) 322 Page - Texas Instruments |
|
|
322 / 427 page  mmcj_clk mmcj_cmd mmcj_dat[3:0] SDR504 SDR508 SDR503 SDR507 SDR501 SDR502H SDR502L MMC3/4_05 mmcj_clk mmcj_cmd mmcj_dat[3:0] SDR251 SDR252L SDR252H SDR255 SDR256 SDR255 SDR256 MMC3/4_14 322 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Figure 7-82. .MMC/SD/SDIOj in - SDR25 - Transmitter Mode 7.22.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle Figure 7-83, Figure 7-84, Table 7-130, and Table 7-131 present Timing requirements and Switching characteristics for MMC3 - SDIO High speed SDR50 in receiver and transmitter mode. Table 7-130. Timing Requirements for MMC3 - SDR50 Mode (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR503 tsu(cmdV-clkH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 1.48 ns SDR504 th(clkH-cmdV) Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns SDR507 tsu(dV-clkH) Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 1.48 ns SDR508 th(clkH-dV) Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns (1) i in [i:0] = 7 Table 7-131. Switching Characteristics for MMC3 - SDR50 Mode (2) NO. PARAMETER DESCRIPTION MIN MAX UNIT SDR501 fop(clk) Operating frequency, mmc3_clk 64 MHz SDR502 H tw(clkH) Pulse duration, mmc3_clk high 0.5*P- 0.270 (1) ns SDR502L tw(clkL) Pulse duration, mmc3_clk low 0.5*P- 0.270 (1) ns SDR505 td(clkL-cmdV) Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -3.66 1.46 ns SDR506 td(clkL-dV) Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -3.66 1.46 ns (1) P = output mmc3_clk period in ns (2) i in [i:0] = 7 Figure 7-83. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
