TDA2SA datasheet(331/427 Pages) TI2

331 / 427 page

SPRABP6-002

TOP/SIGNAL1

GROUND

POWER

SIGNAL2

SIGNAL3

POWER

GROUND

BOTTOM/SIGNAL4

Package

DIE

Trace

Capacitor

Via

Note: 1. BGA via pair loop inductance

2. Power/Ground net spreading inductance

3. Capacitor trace inductance

Loop inductance

Power/Ground

Ground/Power

SPRABP6-001

331

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

www.ti.com

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

Submit Documentation Feedback

Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

Figure 8-1. Minimize Loop Inductance With Proper Layer Assignment

The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a

significant impact on the parasitic inductances of power current path as shown in Figure 8-1. For this

reason, it is recommended to consider layer order in the early stages of the PCB PDN design cycle,

putting high-priority supplies in the top half of the stackup (assuming high load and priority components

are mounted on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown

in the examples below (vias have parasitic inductances which impact the bottom layers more, so it is

advised to put the sensitive and high-priority power supplies on the top/same layers).

Two PCB stack-ups with layer assignments and via types that can enable an optimize PDN are shown in

Figure 8-2 and Figure 8-3.

Figure 8-2. Layer PCB With High Density Interconnect (HDI) Vias

TDA2SA Datasheet(PDF) 331 Page - Texas Instruments