TDA2SA datasheet(332/427 Pages) TI2

332 / 427 page

SPRABP6-003

TOP/SIGNAL1

POWER

GROUND

SIGNAL2

SIGNAL3

GROUND

POWER

BOTTOM/SIGNAL4

332

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

Figure 8-3. Layer PCB With Plated Through Holes (PTH) Vias

8.2.2

Step 2: Physical Placement

A critical step in designing an optimized PDN is that proper care must be taken to making sure that the

initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The

following points are important for optimizing a PCB’s PDN:

•

Minimizing the physical distance between power sources and key high load components is the first

step toward optimization. Placing source and load components on the same side of the PCB is

desirable. This will minimize via inductance impact for high current loads and steps

•

External trace routing between components must be as wide as possible. The wider the traces, the

lower the DC resistance and consequently the lower the static IR drop.

•

Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are

preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance

and improved high frequency performance of the PDN.

•

Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling

capacitors, power inductors and current sensing resistors). Do not share vias among multiple

capacitors for connecting power supply and ground planes.

•

Placement of vias must be as close as possible or even within a component’s solder pad if the PCB

technology you are using provides this capability.

Figure 8-4 shows an example of acceptable width for power net routing but with poor via placement.

TDA2SA Datasheet(PDF) 332 Page - Texas Instruments

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