TDA2SA datasheet(336/427 Pages) TI2

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BGA pad on PCB

Source

Component

Load

Component

Static IR drop and Effective Resistance

PCB

PCB_PO_10

336

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

Figure 8-10. Static IR Drop Budget for PCB Only

The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR

or DC analysis/design methodology consists of designing the PDN such that the voltage drop (under DC

operating conditions) across power and ground pads of the transistors of the application processor device

is within a specified value of the nominal voltage for proper functionality of the device.

A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal

voltage. For a 1.35-V supply, this would be

≤20 mV.

To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and

simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration

violations of current-carrying vias, and “Swiss-cheese” effects via placement has on power rails. It is

recommended to perform the following analyses:

•

Lumped resistance/IR drop analysis

•

Distributed resistance/IR drop analysis

NOTE

The PMIC companion device supporting Processor has been designed with voltage sensing

feedback loop capabilities that enable a remote sense of the SMPS output voltage at the

point of use.

The NOTE above means the SMPS feedback signals and returns must be routed across PCB and

connected to the Device input power ball for which a particular SMPS is supplying power. This feedback

loop provides compensation for some of the voltage drop encountered across the PDN within limits. As

such, the effective resistance of the PDN within this loop should be determined in order to optimize

voltage compensation loop performance. The resistance of two PDN segments are of interest: one from

the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the

entire PDN route from SMPS output pin/ball to the Processor input power.

In the following sections each methodology is described in detail and an example has been provided of

analysis flow that can be used by the PCB designer to validate compliance to the requirements on their

PCB PDN design.

8.2.3.1

PDN Resistance and IR Drop

Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and

processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and

the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance

for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,

shape, length, via count and placement Figure 8-11 illustrates the pin-grouping/lumped concept.

TDA2SA Datasheet(PDF) 336 Page - Texas Instruments

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