TDA2SA datasheet(339/427 Pages) TI2

339 / 427 page

Trace

Pad

Via

Mounting geometry for reduced inductance

Via-in-pad

SWPS040-177

339

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

www.ti.com

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance

of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize

distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.

Further improvements can be made to the mounting by placing vias to the side of capacitor lands or

doubling the number of vias as shown in Figure 8-15. If the PCB manufacturing processes allow it and if

cost-effective, via-in-pad (VIP) geometries are strongly recommended.

In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the

effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the

capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on

the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z

is due to PCB thickness (as shown in Figure 8-2).

From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in Figure 8-

15 are known as:

•

2-via, Skinny End Exit (2vSEE)

•

2-via, Wide End Exit (2vWEE)

•

2-via, Wide Side Exit (2vWSE)

•

4-via, Wide Side Exit (4vWSE)

•

2-via, In-Pad (2vIP)

Figure 8-15. Capacitor Placement Geometry for Improved Mounting Inductance

NOTE

Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)

vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was

used in place of 2vSEE.

Decoupling Capacitor (Dcap) Strategy:

1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and

layout area in order to minimize Dcap loop inductance to power pin as much as possible (see Figure 8-

15).

2. Place Dcaps on “same-side” as component within their power plane outline to minimize “decoupling

loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB

layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify

TDA2SA Datasheet(PDF) 339 Page - Texas Instruments

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