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TDA2SA Datasheet(PDF) 397 Page - Texas Instruments

Part # TDA2SA
Description  TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0
PDF  427 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDA2SA Datasheet(HTML) 397 Page - Texas Instruments

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397
TDA2SX, TDA2SG, TDA2SA
TDA2HG, TDA2HV, TDA2HF, TDA2LF
www.ti.com
SPRS951F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF
Applications, Implementation, and Layout
Copyright © 2015–2019, Texas Instruments Incorporated
8.7.3.5
Compatible JEDEC DDR3 Devices
Table 8-44 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1066 devices in the x8 or x16 widths.
Table 8-44. Compatible JEDEC DDR3 Devices (Per Interface)
N
O.
PARAMETER
CONDITION
MIN
MAX
UNIT
1
JEDEC DDR3 device speed grade(1)
DDR clock rate = 400MHz
DDR3-800
DDR3-1600
400MHz< DDR clock rate
≤ 533MHz
DDR3-1066
DDR3-1600
2
JEDEC DDR3 device bit width
x8
x16
Bits
3
JEDEC DDR3 device count(2)
2
4
Devices
(1) Refer to Table 8-42 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see Section 8.7.3.4, Figure 8-58, and Figure 8-59.
8.7.3.6
PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-45.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in
Table 8-46.
Table 8-45. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly vertical
2
Plane
Ground
3
Plane
Split power plane
4
Plane
Split power plane or Internal routing
5
Plane
Ground
6
Signal
Bottom routing mostly horizontal



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