TDA2SA datasheet(400/427 Pages) TI2

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DDR3 Keepout Region

DDR3

Controller

PCB_DDR3_4

400

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

(1) DDR3 keepout region to encompass entire DDR3 routing area.

(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.

(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be

separated by this specification.

8.7.3.8

DDR3 Keepout Region

The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout

region is defined for this purpose and is shown in Figure 8-61. The size of this region varies with the

placement and DDR routing. Additional clearances required for the keepout region are shown in Table 8-

47. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.

Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the

DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this

region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the

two signals from the DDR3 controller should be separated from each other by the specification in Table 8-

47, (see KOD37).

Figure 8-61. DDR3 Keepout Region

8.7.3.9

Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.

Table 8-48 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk

bypass capacitance may be needed for other circuitry.

TDA2SA Datasheet(PDF) 400 Page - Texas Instruments