TDA2SA datasheet(402/427 Pages) TI2

402 / 427 page

402

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

8.7.3.10.1 Return Current Bypass Capacitors

Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals

hopping from one signal layer to another. The bypass capacitor here provides a path for the return current

to hop planes along with the signal. As many of these return current bypass capacitors should be used as

possible. Because these are returns for signal current, the signal via size may be used for these

capacitors.

8.7.3.11 Net Classes

Table 8-50 lists the clock net classes for the DDR3 interface. Table 8-51 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-50. Clock Net Class Definitions

CLOCK NET CLASS

processor PIN NAMES

DDR[x]_CLK/DDR[x]_CLK

DQS0

DDR[x]_DQS[0]/DDR[x]_DQS[0]

DQS1

DDR[x]_DQS[1]/DDR[x]_DQS[1]

DQS2(1)

DDR[x]_DQS[2]/DDR[x]_DQS[2]

DQS3(1)

DDR[x]_DQS[3]/DDR[x]_DQS[3]

(1) Only used on 32-bit wide DDR3 memory systems.

Table 8-51. Signal Net Class Definitions

SIGNAL NET CLASS

ASSOCIATED CLOCK

NET CLASS

processor PIN NAMES

ADDR_CTRL

DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,

DDR[x]_WE, DDR[x]_CKE, DDR[x]_ODT[x]

DQ0

DQS0

DDR[x]_D[7:0], DDR[x]_DQM[0]

DQ1

DQS1

DDR[x]_D[15:8], DDR[x]_DQM[1]

DQ2(1)

DQS2

DDR[x]_D[23:16], DDR[x]_DQM[2]

DQ3(1)

DQS3

DDR[x]_D[31:24], DDR[x]_DQM[3]

(1) Only used on 32-bit wide DDR3 memory systems.

8.7.3.12 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

8.7.3.13 VREF_DDR Routing

ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the

processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the

DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF

bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing

congestion.

8.7.3.14 VTT

Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is

expected to source and sink current, specifically the termination current for the ADDR_CTRL net class

Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power

sub-plane. VTT should be bypassed near the terminator resistors.

TDA2SA Datasheet(PDF) 402 Page - Texas Instruments

TDA2SA Datasheet(HTML) 402 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL