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TDA2SA Datasheet(PDF) 406 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 406 Page - Texas Instruments |
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406 / 427 page  A1 A2 Processor Address and Control Output Buffer DDR Address and Control Input Buffers A3 AT VTT Address and Control Terminator Rtt A1 A2 Processor Differential Clock Output Buffer DDR Differential CK Input Buffers Routed as Differential Pair A3 AT Rcp Clock Parallel Terminator A1 A2 A3 AT Rcp Cac DDR_1V5 0.1 µF + – + – + – 406 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Applications, Implementation, and Layout Copyright © 2015–2019, Texas Instruments Incorporated Figure 8-68. CK Topology for Two DDR3 Devices Figure 8-69. ADDR_CTRL Topology for Two DDR3 Devices 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices Figure 8-70 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-71 shows the corresponding ADDR_CTRL routing. |
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