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TDA2SA Datasheet(PDF) 403 Page - Texas Instruments

Part # TDA2SA
Description  TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0
PDF  427 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDA2SA Datasheet(HTML) 403 Page - Texas Instruments

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A1
A2
Processor
Address and Control
Output Buffer
DDR Address and Control Input Buffers
A3
A4
A3
AT
VTT
Address and Control
Terminator
Rtt
A1
A2
Processor
Differential Clock
Output Buffer
DDR Differential CK Input Buffers
Routed as Differential Pair
A3
A4
A3
AT
Rcp
Clock Parallel
Terminator
A1
A2
A3
A4
A3
AT
Rcp
Cac
DDR_1V5
0.1 µF
+
–
+ –
+ –
+ –
+ –
403
TDA2SX, TDA2SG, TDA2SA
TDA2HG, TDA2HV, TDA2HF, TDA2LF
www.ti.com
SPRS951F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF
Applications, Implementation, and Layout
Copyright © 2015–2019, Texas Instruments Incorporated
8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed in a fly-by topology. They are routed in a similar manner
and are length matched to minimize skew between them. CK is a bit more complicated because it runs at
a higher transition rate and is differential. The following subsections show the topology and routing for
various DDR3 configurations for CK and ADDR_CTRL. The figures in the following subsections define the
terms for the routing specification detailed in Table 8-52. Balanced-T routing is not recommended.
8.7.3.15.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
Figure 8-62 shows the topology of the CK net classes and Figure 8-63 shows the topology for the
corresponding ADDR_CTRL net classes.
Figure 8-62. CK Topology for Four x8 DDR3 Devices
Figure 8-63. ADDR_CTRL Topology for Four x8 DDR3 Devices
8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
Figure 8-64 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-65
shows the corresponding ADDR_CTRL routing.



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