TDA2SA datasheet(410/427 Pages) TI2

410 / 427 page

Rtt

VTT

Rcp

Cac

DDR_1V5

0.1 µF

410

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

Figure 8-76. CK Routing for One DDR3 Device

Figure 8-77. ADDR_CTRL Routing for One DDR3 Device

8.7.3.16 Data Topologies and Routing Definition

No matter the number of DDR3 devices used, the data line topology is always point to point, so its

definition is simple.

Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is

better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure

there are nearby ground vias to allow the return currents to transition between reference planes if both

reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return

currents to transition between reference planes if one of the reference planes is ground. The goal is to

minimize the size of the return current loops.

8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices

DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-78

and Figure 8-79 show these topologies.

TDA2SA Datasheet(PDF) 410 Page - Texas Instruments