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DDR_CLK

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SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

(1) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated

DQS (2 DQSs) per DDR EMIF used.

(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS

(4 DQSs) per DDR EMIF used.

(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data

byte 1.

(5) DQs from other DQS domains are considered other DDR2 trace.

(6) DQs from other data bytes are considered other DDR2 trace.

(7) This is the longest routing distance of each of the DQS and DQ net classes.

8.7.3

DDR3 Board Design and Layout Guidelines

8.7.3.1

Board Designs

TI only supports board designs using DDR3 memory that follow the guidelines in this document. The

switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-42 and

Figure 8-57.

Table 8-42. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory

Controller

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CLK)

Cycle time, DDR_CLK

1.875

2.5(1)

(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and

operating frequency (see the DDR3 memory device data sheet).

Figure 8-57. DDR3 Memory Controller Clock Timing

8.7.3.1.1 DDR3 versus DDR2

This specification only covers device PCB designs that use DDR3 memory. Designs using DDR2 memory

should use the PCB design specifications for DDR2 memory. While similar, the two memory systems have

different requirements. It is currently not possible to design one PCB that covers both DDR2 and DDR3.

8.7.3.2

DDR3 EMIFs

The processor contains two separate DDR3 EMIFs. This specification covers one of these EMIFs (ddr1_*)

and, thus, needs to be implemented twice, once for each EMIF. The PCB layout generally turns out to be

a semi-mirror with ddr2_* being a flipped version of ddr1_*; the only exception being the DDR3 devices

themselves are not flipped unless mounted on opposite sides of the PCB. Requirements are identical

between the two EMIFs.

8.7.3.3

DDR3 Device Combinations

Because there are several possible combinations of device counts and single- or dual-side mounting,

Table 8-43 summarizes the supported device configurations.

Table 8-43. Supported DDR3 Device Combinations(1)

NUMBER OF DDR3 DEVICES

DDR3 DATA DEVICE WIDTH

(BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

Y(2)

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