TDA2SA datasheet(389/427 Pages) TI2

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389

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

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SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,

and processor/DDR ground connections. Table 8-36 contains the specification for the HS bypass

capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

1. Fit as many HS bypass capacitors as possible.

2. HS bypass capacitor value is < 1µF

3. Minimize the distance from the bypass cap to the pins/balls being bypassed.

4. Use the smallest physical sized capacitors possible with the highest capacitance readily available.

5. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest

hole size via possible.

6. Minimize via sharing. Note the limites on via sharing shown in Table 8-36.

Table 8-36. High-Speed Bypass Capacitors

NO.

PARAMETER

MIN

TYP

MAX

UNIT

HS21

HS bypass capacitor package size(1)

0201

0402

10 Mils

HS22

Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)

400(12)

Mils

HS23

processor HS bypass capacitor count (12)

See Table 8-3 and (11)

Devices

HS24

processor HS bypass capacitor total capacitance per vdds_ddrx rail

(12)

See Table 8-3 and (11)

μF

HS25

Number of connection vias for each device power/ground ball per

vdds_ddrx rail (5)

Vias

HS26

Trace length from device power/ground ball to connection via(2)

Mils

HS27

Distance, HS bypass capacitor to DDR device being bypassed(6)

150

Mils

HS28

Number of connection vias for each HS capacitor(8)(9)

4 (14)

Vias

HS29

DDR2 device HS bypass capacitor count(7)

12 (13)

Devices

HS210

DDR2 device HS bypass capacitor total capacitance(7)

0.85

μF

HS211

Trace length from bypass capacitor connect to connection via(2)(9)

100

Mils

HS212

Number of connection vias for each DDR2 device power/ground

ball(10)

Vias

HS213

Trace length from DDR2 device power/ground ball to connection

via(2)(8)

Mils

(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.

(2) Closer/shorter is better.

(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.

(4) Three of these capacitors should be located underneath the processor, between the cluster of vdds_ddrx balls and ground balls,

between the DDR interfaces on the package.

(5) See the Via Channel™ escape for the processor package.

(6) Measured from the DDR2 device power/ground ball to the center of the capacitor package.

(7) Per DDR2 device.

(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of

vias is permitted on the same side of the board.

(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the

connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.

(10) Up to a total of two pairs of DDR power/ground balls may share a via.

(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s

guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.

(12) For more information, see Section 8.3, Core Power Domains

(13) For more information refer to DDR2 specification.

(14) Preferred configuration is 4 vias: 2 to power and 2 to ground.

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