TDA2SA datasheet(385/427 Pages) TI2

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385

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

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SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

8.7.2.2.2 Compatible JEDEC DDR2 Devices

Table 8-31 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.

Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.

Table 8-31. Compatible JEDEC DDR2 Devices (Per Interface)

NO.

PARAMETER

MIN

MAX

UNIT

CJ21

JEDEC DDR2 device speed grade(1)

DDR2-800

CJ22

JEDEC DDR2 device bit width

x16

Bits

CJ23

JEDEC DDR2 device count(2)

Devices

CJ24

JEDEC DDR2 device ball count(3)

Balls

(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.

(2) One DDR2 device is used for a 16-bit DDR2 memory system. Two DDR2 devices are used for a 32-bit DDR2 memory system.

(3) The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball

DDR2 devices are the same.

8.7.2.2.3 PCB Stackup

The minimum stackup required for routing the Device is a six-layer stackup as shown in Table 8-32.

Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the size

of the PCB footprint.

Table 8-32. Minimum PCB Stackup

LAYER

TYPE

DESCRIPTION

Signal

Top routing mostly horizontal

Plane

Ground

Plane

Power

Signal

Internal routing

Plane

Ground

Signal

Bottom routing mostly vertical

TDA2SA Datasheet(PDF) 385 Page - Texas Instruments

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