TDA2SA datasheet(382/427 Pages) TI2

382 / 427 page

382

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

8.7.2.2

DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need

for a complex timing closure process. For more information regarding the guidelines for using this DDR2

specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification.

8.7.2.2.1 DDR2 Interface Schematic

Figure 8-50 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-51 the x16

DDR2 system schematic is identical except that the high-word DDR2 device is deleted.

When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off

the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding

vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. The vdds_ddrx and

ddrx_vref0 power supply pins need to be connected to their respective power supplies even if DDRx is not

being used. All other DDR interface pins can be left unconnected. Note that the supported modes for use

of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.

TDA2SA Datasheet(PDF) 382 Page - Texas Instruments