TDA2SA datasheet(378/427 Pages) TI2

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378

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.

8.5.6.2.2 Routing Specifications

8.5.6.2.2.1 Impedance

The PCIe data signal traces must be routed to achieve 100-Ω (±10%) differential impedance and 60-Ω

(±10%) single-ended impedance. The single-ended impedance is required because differential signals are

extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.

These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0

document, available from PCI-SIG (www.pcisig.com).

These impedances are impacted by trace width, trace spacing, distance between signals and referencing

planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal

pairs result in as close to 100-Ω differential impedance and 60-Ω single-ended impedance as possible. For

best accuracy, work with your PCB fabricator to ensure this impedance is met. See Table 8-26 below.

8.5.6.2.2.2 Differential Coupling

In general, closely coupled differential signal traces are not an advantage on PCBs. When differential

signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing

variations affect impedance dramatically, so tight impedance control can be more problematic to maintain

in production. For PCBs with very tight space limitations (which are usually small) this can work, but for

most PCBs, the loosely coupled option is probably best.

Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing

make obstacle avoidance easier (because each trace is not so fixed in position relative to the other), and

trace width variations don’t affect impedance as much, therefore it’s easier to maintain an accurate

impedance over the length of the signal. For longer routes, the wider traces also show reduced skin effect

and therefore often result in better signal integrity with a larger eye diagram opening.

Table 8-26 shows the routing specifications for the PCIe data signals.

Table 8-26. PCI-E Routing Specifications

PARAMETER

MIN

TYP

MAX

UNIT

PCIe signal trace length (device balls to PCIe connector)

4700(1)

Mills

Differential pair trace matching

5(2)

Mils

Number of stubs allowed on PCIe traces(3)

stubs

TX/RX pair differential impedance

100

110

TX/RX single-ended impedance

Pad size of vias on PCIe trace

25(4)

Mils

Hole size of vias on PCIe trace

Mils

Number of vias on each PCIe trace

Vias

PCIe differential pair to any other trace spacing

2×DS(5)

(1) Beyond this, signal integrity may suffer.

(2) For example, RXP0 within 5 Mils of RXN0.

(3) Inline pads may be used for probing.

(4) 35-Mil antipad maximum recommended.

(5) DS = differential spacing of the PCIe traces.

Table 8-27. PCI-E Routing Recommendations

Item

Description

Reason

ESD part number

None

ESD suppression generally not

used on PCIe

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