TDA2SA datasheet(381/427 Pages) TI2

381 / 427 page

ddrx_ck

PCB_DDR2_0

xi_oscj

vssa_oscj

Device

xo_oscj

Crystal

(Optional)

SPRS85v_PCB_CLK_OSC_3

381

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

www.ti.com

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

(1)

j in *_osc = 0 or 1

Figure 8-48. Grounding Scheme for High-Frequency Clock

8.7

DDR2/DDR3 Board Design and Layout Guidelines

8.7.1

DDR2/DDR3 General Board Layout Guidelines

To help ensure good signaling performance, consider the following board design guidelines:

•

Avoid crossing splits in the power plane.

•

Minimize Vref noise.

•

Use the widest trace that is practical between decoupling capacitors and memory module.

•

Maintain a single reference.

•

Minimize ISI by keeping impedances matched.

•

Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.

•

Use proper low-pass filtering on the Vref pins.

•

Keep the stub length as short as possible.

•

Add additional spacing for on-clock and strobe nets to eliminate crosstalk.

•

Maintain a common ground reference for all bypass and decoupling capacitors.

•

Take into account the differences in propagation delays between microstrip and stripline nets when

evaluating timing constraints.

8.7.2

DDR2 Board Design and Layout Guidelines

8.7.2.1

Board Designs

TI only supports board designs that follow the guidelines outlined in this document. The switching

characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-30 and

Figure 8-49.

Table 8-30. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory

Controller

NO.

PARAMETE

DESCRIPTION

MIN

MAX

UNIT

DDR21

tc(DDR_CLK)

Cycle time, DDR_CLK

2.5

Figure 8-49. DDR2 Memory Controller Clock Timing

TDA2SA Datasheet(PDF) 381 Page - Texas Instruments

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