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TDA2SA Datasheet(PDF) 391 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 391 Page - Texas Instruments |
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391 / 427 page ![]() PCB_DDR2_6 DDR2 Controller B C A’ A” T PCB_DDR2_5 DDR2 Controller VREF Bypass Capacitor Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. VREF Nominal Max Trace width is 20 mils 391 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Applications, Implementation, and Layout Copyright © 2015–2019, Texas Instruments Incorporated Figure 8-54. VREF Routing and Topology 8.7.2.3 DDR2 CK and ADDR_CTRL Routing Figure 8-55 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A = (A'+A'') should be maximized. Figure 8-55. CK and ADDR_CTRL Routing and Topology Table 8-40. CK and ADDR_CTRL Routing Specification (1) NO. PARAMETER MIN MAX UNIT RSC21 Center-to-center ddrx_ck - ddrx_nck spacing 2w RSC22 ddrx_ck / ddrx_nck skew(1) 5 ps RSC23 CK A-to-B/A-to-C skew mismatch(2) 10 ps |
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