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TDA2SA Datasheet(PDF) 117 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 117 Page - Texas Instruments |
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117 / 427 page  117 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-15. Universal Serial Bus Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL usb4_ulpi_dir USB4 - ULPI bus direction I V7 usb4_ulpi_stp USB4 - ULPI stop O V9 usb4_ulpi_clk USB4 - ULPI functional clock I W9 4.4.13 SATA NOTE For more information, see the Serial Communication Interfaces / SATA section of the device TRM. Table 4-16. SATA Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL sata1_rxn0 SATA differential negative receiver lane 0 IDS AH9 sata1_rxp0 SATA differential positive receiver lane 0 IDS AG9 sata1_txn0 SATA differential negative transmitter lane 0 ODS AG10 sata1_txp0 SATA differential positive transmitter lane 0 ODS AH10 sata1_led SATA channel activity indicator O A22 / G19 4.4.14 Peripheral Component Interconnect Express (PCIe) NOTE For more information, see the Serial Communication Interfaces / PCIe section of the device TRM. Table 4-17. PCIe Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL pcie_rxn0 PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only. IDS AG13 pcie_rxp0 PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only. IDS AH13 pcie_txn0 PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only. ODS AG14 pcie_txp0 PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only. ODS AH14 pcie_rxn1 PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IDS AG11 pcie_rxp1 PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IDS AH11 pcie_txn1 PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AG12 pcie_txp1 PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AH12 ljcb_clkp PCIe1_PHY shared Reference Clock Input / Output Differential Pair (positive) IODS AG15 ljcb_clkn PCIe1_PHY shared Reference Clock Input / Output Differential Pair (negative) IODS AH15 |
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