Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

TMP42x-Q1

ACK By

TMP42x-Q1

Frame 3 Two-Wire Slave Address Byte

Frame 4 Data Byte 1 Read Register

Start By

Master

ACK By

TMP42x-Q1

ACK By

Master

From

TMP42x-Q1

1

9

1

9

1

9

1

9

SDA

SCL

0

0

1

R/W

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

¼

¼

SDA

(Continued)

SCL

(Continued)

SDA

(Continued)

SCL

(Continued)

1

0

0

1

1

0

0

(1)

1

0

0

(1)

R/W

D7

D6

D5

D4

D3

D2

D1

D0

Frame 5 Data Byte 2 Read Register

Stop By

Master

NACK By

Master

(2)

From

TMP42x-Q1

1

9

D7

D6

D5

D4

D3

D2

D1

D0

17

TMP421-Q1, TMP422-Q1, TMP423-Q1

www.ti.com

SBOS821 – NOVEMBER 2016

Product Folder Links: TMP421-Q1 TMP422-Q1 TMP423-Q1

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Copyright © 2016, Texas Instruments Incorporated

Programming (continued)

(1)

Slave address 1001100 shown.

(2)

The master must leave the SDA high to terminate a two-byte read operation.

Figure 17. Two-Wire Timing Diagram for Two-Byte Read Format

8.5.4 Serial Bus Address

To communicate with the TMP421-Q1, TMP422-Q1, and TMP423-Q1, the master must first address slave

devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit

indicating the intent of executing a read or write operation.

8.5.5 Two-Wire Interface Slave Device Addresses

The TMP421-Q1 supports nine slave device addresses and the TMP422-Q1 supports four slave device

addresses. The TMP423-Q1 has one of two factory-preset slave addresses.

The slave device address for the TMP421-Q1 is set by the A1 and A0 pins according to Table 3.

The slave device address for the TMP422-Q1 is set by the connections between the external transistors and the

TMP422-Q1 according to Figure 18 and Table 4. If one of the channels is unused, the respective DXP

connection must be connected to GND, and the DXN connection must be left unconnected. The polarity of the

transistor for external channel 2 (pins 3 and 4) sets the least significant bit of the slave address. The polarity of

the transistor for external channel 1 (pins 1 and 2) sets the next least significant bit of the slave address.