P

S

P

S

VIH

VIL

SCL

VIH

VIL

SDA

tBUF

tHD;STA

tLOW

tR

tHD;DAT

tHIGH

tF

tSU;DAT

tSU;STA

tSU;STO

tVD;DAT

7

TMP421-Q1, TMP422-Q1, TMP423-Q1

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SBOS821 – NOVEMBER 2016

Product Folder Links: TMP421-Q1 TMP422-Q1 TMP423-Q1

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(1)

The maximum tHD;DAT can be 0.9 μs for Fast-Mode, and is less than the maximum tVD;DAT by a transition time.

(2)

tVDDATA = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).

7.6 Timing Requirements

at –40°C to +125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted); values are based on statistical analysis of samples

tested during initial release

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

f(SCL)

SCL operating frequency

0.001

0.4

0.001

2.56

MHz

t(BUF)

Bus free time between STOP and START condition

1300

160

ns

t(HD;STA)

Hold time after repeated START condition.

After this period, the first clock is generated.

600

160

ns

t(SU;STA)

Repeated START condition setup time

600

160

ns

t(SU;STO)

STOP condition setup time

600

160

ns

t(HD;DAT)

Data hold time

25

See (1)

5

90

ns

t(VD.DAT)

Data valid time (data response time)(2)

900

Not applicable

ns

t(SU;DAT)

Data setup time

100

10

ns

t(LOW)

SCL clock LOW period

1300

250

ns

t(HIGH)

SCL clock HIGH period

600

60

ns

tF – SDA

Data fall time

300

150

ns

tF – SCL

Clock fall time

300

40

ns

tR

Clock, data rise time

1000

ns

Serial bus timeout

25

35

25

35

ms

Figure 1. Two-Wire Timing Diagram