JMS583

Datasheet

Revision 1.0

8

Document No.: PDS-17001

The information contained in this document is the exclusive property of JMicron Technology Corporation and shall not be used,

collected, reproduced, distributed and/or disclosed in whole or in part without prior written permission of JMicron Technology

Corporation.

5.3 Pin description

5.3.1 PCIe interface

Table 2

Pin description

– PCIe interface

Signal Name

QFN 64

Type

Description

P_RXN1

34

AI

PCIe Port RX- Signal of Lane 1

P_RXP1

35

AI

PCIe Port RX+ Signal of Lane 1

P_TXN1

37

AO

PCIe Port TX- Signal of Lane 1

A 220 nF capacitor should be connected between this pin and PCIe

connector.

P_TXP1

38

AO

PCIe Port TX+ Signal of Lane 1

A 220 nF capacitor should be connected between this pin and PCIe

connector.

REXT

39

AI

External Reference Resistance

A 12 k

1% external resistor should be connected to this pin.

P_RXN0

41

AI

PCIe Port RX- Signal of Lane 0

P_RXP0

42

AI

PCIe Port RX+ Signal of Lane 0

P_TXN0

44

AO

PCIe Port TX- Signal of Lane 0

A 220 nF capacitor should be connected between this pin and PCIe

connector.

P_TXP0

45

AO

PCIe Port TX+ Signal of Lane 0

A 220 nF capacitor should be connected between this pin and PCIe

connector.

CLKP

48

DO

Differential Clock P

100Mhz reference clock for Device.

CLKN

47

DO

Differential Clock N

100Mhz reference clock for Device.

P_RSTN

54

DO

PCIE Reset for Device

P_CLKREQN

55

DIO

This is for L1 substate