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LM4931 Datasheet(PDF) 14 Page - National Semiconductor (TI) |
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LM4931 Datasheet(HTML) 14 Page - National Semiconductor (TI) |
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14 / 48 page  Basic Configuration Register This register used to configure the basic function of the chip. DEFAULT CHART FOR BASIC_CONFIG (00h) DATA BIT 7 6 5 4 3 2 1 0 DEFAULT 0 0 0 0 0 0 0 0 BASIC_CONFIG (00h) (SET = LOGIC 1, CLEAR = LOGIC 0) Address Register Description 3:0 MODE The LM4931 can be placed in one of several modes that dictate the basic operation. When a new mode is selected the LM4931 will change operation silently and will reconfigure the power management profile automatically. The modes are described as follows: (Note 13) 3:0 Mono Speaker Amplifier Source Headphone Left Source Headphone Right Source Comment 0000 None None None Powerdown mode 0001 None None None Standby mode 0010 Voice None None Mono speaker mode 0011 None Voice Voice Headphone call mode 0100 Voice Voice Voice Conference call mode 0101 Audio (L+R) None None L+R mixed to mono speaker 0110 None Audio (Left) Audio (Right) Headphone stereo audio 0111 Audio (L+R) Audio (Left) Audio (Right) L+R mixed to mono speaker + stereo headphone audio 1000 Audio (Left) Voice Voice Mixed mode 1001 Voice + Audio (Left) Voice Voice Mixed mode 1010 Voice Audio (Left) Audio (Left) Mixed mode 4 SOFTRESET If set, resets the LM4931, excluding the I 2C/SPI registers and PLL. SOFTRESET should be cleared to resume normal operation. 5 DAC_ DITHER_OFF Disables the audio DAC dither. 6 BYPASS_BYPASS If set the power management and control circuit will assume that bypass is at V DD/2 even when such condition is false. (Note 12) 7 RSVD RESERVED (Note 14) Note 12: It is recommended to alter this bit only while the part is in Powerdown mode. Note 13: Modes 8, 9, and 10 are only available if the sample rate of the I2S is an integer multiple of the sample rate of the PCM. For example, 48kHz (I2S) and 8kHz (PCM) would be acceptable. Note 14: Reserved bits should be set to zero when programming the associated register. www.national.com 14 |
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