TABLE 12. Analog Input Amplifier Gain Select

MONO_IN_GAIN_2

ANA_L_GAIN_2

ANA_R_GAIN_2

MONO_IN_GAIN_1

ANA_L_GAIN_1

ANA_R_GAIN_1

MONO_IN_GAIN_0

ANA_L_GAIN_0

ANA_R_GAIN_0

Input Gain Setting

000

–6dB

001

–3dB

010

0dB

011

3dB

100

6dB

101

9dB

1

1

0

12dB

1

1

1

15dB

TABLE 13. DAC Gain Select

DIG_L_GAIN_1

DIG_R_GAIN_1

DIG_L_GAIN_1

DIG_R_GAIN_1

Input Gain Setting

0

0

–3dB

0

1

0dB

1

0

3dB

1

1

6dB

PLL Configuration Registers

PLL M DIVIDER CONFIGURATION REGISTER

This register is used to control the input divider of the PLL.

PLL_M (0Ah) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

6:0

PLL_M

Programs the PLL input divider to select:

PLL_M

Divide Ratio

0

Divider Off

11

2

1.5

32

4

2.5

...

3

→

126

63.5

127

64

NOTES:

The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details.

The divider of the M divider is derived from PLL_M as such:

M = (PLL_M+1) / 2

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