Fs (kHz)

DAC Oversampling Ratio

Required CLock at DAC Clock Generator Input (MHz)

44.1

125

11.025

44.1

128

11.2896

48

125

12

48

128

12.288

88.2

64

11.2896

96

64

12.288

176.4

32

22.5792

192

32

24.576

Methods for producing these clock frequencies are described in the PLL section.

The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table

below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we

can save power and the clock jitter will be low.

R_DIV

Divide Value

11

6

2

8

9

5

2.4

9.6

74

3

12

53

4

16

4

2.5

4.8

19.2

32

6

24

2

1.5

8

32

0

1

12

48

The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates.

DAC Setup Register

This register is used to configure the basic operation of the stereo DAC.

DAC_SETUP (0Eh)

(Set = logic 1, Clear = logic 0)

Bits

Register

Description

1:0

DAC_MODE

The DAC used in the LM4934 can operate in one of 4 oversampling modes.

The modes are described as follows:

DAC_MODE

Oversampling

Rate

Typical FS

Clock Required

00

125

48KHz

12.000MHz (USB

Mode)

01

128

44.1KHz

48KHz

11.2896MHz

12.288MHz

10

64

96KHz

12.288MHz

11

32

192KHz

24.576MHz

2

MUTE_L

Mutes the left DAC channel on the next zero crossing.

3

MUTE_R

Mutes the right DAC channel on the next zero crossing.

4

DITHER_OFF

If set the dither in DAC is disabled.

5

DITHER

ALWAYS_ON

If set the dither in DAC is enabled all the time.

6

CUST_COMP

If set the DAC frequency response can be programmed manually via a 5 tap FIR

“compensation” filter. This can be used to enhance the frequency response of

small loudspeakers or provide a crude tone control. The compensation

Coefficients can be set by using registers 10h to 15h.

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