PLL N DIVIDER CONFIGURATION REGISTER

This register is used to control PLL N divider.

PLL_N (0Bh) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

7:0

PLL_N

Programs the PLL feedback divider:

PLL_N

Divide Ratio

0

Divider Off

1

→ 10

10

11

11

12

12

...

...

248

248

249

249

250

→ 255

250

NOTES:

The divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so

The non-sigma-delta division of the N divider is derived from the PLL_N as such:

N = PLL_N

PLL P DIVIDER CONFIGURATION REGISTER

This register is used to control the PLL’s P divider.

PLL_P (0Dh) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

3:0

PLL_P

Programs the PLL input divider to select:

PLL_P

Divide Ratio

0

Divider Off

11

2

1.5

32

...

13

7

14

7.5

15

8

NOTES:

The division of the P divider is derived from PLL_P as such:

P = (PLL_P+1) / 2

www.national.com

19