Further Notes on PLL Programming

The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors

noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz

sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x

oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should

be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a

clock that is accurate to within typical crystal tolerances of the real sample rate.

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Example Of Pll Settings For 48Khz Sample Rates

f_in (MHz)

fsamp (kHz)

M

N

P

PLL_M

PLL_N

PLL_N_MOD

PLL_P

f_out (MHz)

11

48

11

60

5

21

60

0

9

12

12

48

5

25

5

9

25

0

9

12

12.288

48

4

19.53125

5

7

19

17

9

12

13

48

13

60

5

25

60

0

9

12

14.4

48

9

37.5

5

17

37

16

9

12

16.2

48

27

100

5

53

100

0

9

12

16.8

48

14

50

5

27

50

0

9

12

19.2

48

13

40.625

5

25

40

20

9

12

19.44

48

27

100

6

53

100

0

11

12

19.68

48

20.5

62.5

5

40

62

16

9

12

19.8

48

16.5

50

5

32

50

0

9

12

Example Pll Settings For 44.1Khz Sample Rates

f_in (MHz)

fsamp (kHz)

M

N

P

PLL_M

PLL_N

PLL_N_MOD

PLL_P

f_out (MHz)

11

44.1

11

55.125

5

21

55

4

9

11.025000

11.2896

44.1

8

39.0625

5

15

39

2

9

11.025000

12

44.1

5

22.96875

5

9

22

31

9

11.025000

13

44.1

13

55.125

5

25

55

4

9

11.025000

14.4

44.1

12

45.9375

5

23

45

30

9

11.025000

16.2

44.1

9

30.625

5

17

30

20

9

11.025000

16.8

44.1

17

55.78125

5

33

55

25

9

11.025000

19.2

44.1

16

45.9375

5

31

45

30

9

11.025000

19.44

44.1

13.5

38.28125

5

26

38

9

9

11.025000

19.68

44.1

20.5

45.9375

4

40

45

30

7

11.025000

19.8

44.1

11

30.625

5

21

30

20

9

11.025000

These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be

done by changing the P divider value or the R divider in the clock configuration diagram.

If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining

11.2896 from 12.000MHz is shown below.

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