for good thermal conduction when operating at high ambient temperatures. If more than one heat-spreading

plane is available, connect them by a number of vias to further improve thermal conduction.

5. Do not socket a high-speed device such as the OPA818. The additional lead length and pin-to-pin

capacitance introduced by the socket potentially creates an extremely troublesome parasitic network that

potentially prevent a smooth, stable frequency response. Best results are obtained by soldering the OPA818

onto the board.

8.4.1.1 Thermal Considerations

The OPA818 does not require heat sinking or airflow in most applications. The maximum allowed junction

temperature sets the maximum allowed internal power dissipation, and is described in the following paragraph.

Do not exceed a maximum junction temperature of 105°C.

The operating junction temperature (TJ) is given by TA + PD × RθJA. The total internal power dissipation (PD)

is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load

power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the

device. The PDL depends on the output signal and load. For a grounded resistive load, the PDL is at a maximum

when the output is fixed at a voltage equal to 1/2 of either supply voltage (for balanced bipolar supplies). Under

this condition, PDL = VS 2 / (4 × RL), where RL includes feedback network loading.

Be aware that the power in the output stage, and not into the load, determines internal power dissipation.

As a worst-case example, compute the maximum TJ using the OPA818 in the circuit of Figure 8-1 operating at a

maximum specified ambient temperature of 85°C and driving a grounded 100-Ω load.

PD = 10 V × 27.7 mA + 52 / (4 × (100 Ω || 350.9 Ω)) ≅ 357 mW

Maximum TJ = 85°C + (0.357 W × 54.6°C/W) = 104.5°C.

In the circuit of Figure 8-1, all practical scenarios are able to operate at a lower internal power and junction

temperature.

8.4.2 Layout Example

Place gain and feedback resistors

close to pins to minimize stray

capacitance

Place bypass capacitor

close to power pins

Connect the thermal pad to a heat

spreading plane, generally ground

1

8

2

7

3

6

4

5

CBYP

RF

RG

RS

CBYP

Thermal

Pad

Connect PD to VS+ to enable the

amplifier

Ground and power plane removed

from inner layers. Ground fill on

outer layers also removed.

Ground and power plane exist on

inner layers.

CBYP

RF

RG

+

–

VS–

CBYP

VS+

Representative schematic

RS

To

Load

No Connect

Figure 8-9. Layout Recommendation

When configuring the OPA818 as a transimpedance amplifier take extra care to minimize the inductance

between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the same side of

the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB increases the parasitic

effects due to via inductance. APD packaging can be quite large, which often requires the APD to be placed

further away from the amplifier than ideal. The added distance between the two device results in increased

inductance between the APD and op-amp feedback network (see also Equation 4). The added inductance is

OPA818

SBOS940B – MAY 2019 – REVISED DECEMBER 2025

www.ti.com

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