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Revision 2.4, May 28, 2002
4 - 7
Hardware Interfaces & Interface Registers
VT1712 - PCI Multi-Channel Audio Controller
CCS08: Consumer AC’97 Index
Address Offset: 08h
Default Value: 00h
CCS09: Consumer AC’97 Command and Status
Address Offset: 09h
Default Value: 00h
CCS0A: Consumer AC’97 Data Port
Address Offset: 0Ah - 0Bh
Default Value: 0000h
Bit
Attribute
Description
7
R0b
-
6:0
R/W
AC’97 registers Index. Refer to the AC’97 specification for register descriptions.
Bit
Attribute
Description
7R/W
Cold reset
W: 1 to cold reset the codec. 0: CRST# will be de-asserted.
6
R/W
Warm reset
W: 1 to warm reset the codec by assertingCSYNC. 0: CSYNC will be de-asserted.
5
R/W
W: 1 to write to AC’97 codec registers
R: 1 indicate the write cycle is still in progress. Cleared when write cycle is complete.
4
R/W
W: 1 to read from AC’97 codec registers
R: 1 indicate the read cycle is still in progress. This bit is cleared when there is valid data.
3
RO
AC’97 codec ready status bit.
After power on, driver should check that this bit is 1 before accessingcodec registers.
2
R0b
-
1
R/W
Enable VSR for Playback (DirectSound accelerator bypassed. Only Channel-E and F active)
0
R/W
Enable VSR for Record (digital return feature automatically disabled)
Bit
Attribute
Description
15:8
R/W
AC’97 codec register data higher byte (index 0Bh)
7:0
R/W
AC’97 codec register data lower byte (index 0Ah)
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