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Revision 2.4, May 28, 2002
4 - 21
Hardware Interfaces & Interface Registers
VT1712 - PCI Multi-Channel Audio Controller
DS4: Channel Data
Address Offset: 04h - 07h
Default Value: 00000000h.
DS8: Channel Index
Address Offset: 08h
Default Value: 00h
Note:
• When the playback enable bit is changed from 0 to 1 (in Index 4 bit 0), the first active buffer will be from buffer 0.
Before this, the return active address and count will not be updated.
Conditions in DMA transfer:
• 16 bit mono: startingaddress is in 2X and count is multiple of 2X bytes (-1)
• 16 bit stereo: startingaddress is in 4X and count is multiple of 4X bytes (-1)
• 8 bit mono: startingaddress is in 1X and count is multiple of 1X bytes (-1)
• 8 bit stereo: startingaddress is in 2X and count is multiple of 2X bytes (-1)
Bit
Attribute
Description
31:0
R/W
Channel Data register. See 32-bit index register description after
Table 4-5.
Bit
Attribute
Description
7:4
R/W
Channel number. Valid only from Channel-0 to D. E and F are reserved for PCM streams regardless
whether runningin native or SB mode.
3:0
R/W
Channel Index register. The table below is used for command decoding purposes.
Table 4-5. DS8 Register, Low Nibble Index Description Applicable to Channel-0 through D
Index
Attribute
Description
0h
R/W
Bits [27:0]
W: Buffer_0 DMA base address[27:0]
R: current active DMA buffer address[27:0]. Byte address.
1h
R/W
Bits [15:0]
W: Buffer_0 DMA base count [15:0]
R: current active DMA count [15:0]. Program byte count minus one.
2h
R/W
Bits[27:0]
W: Buffer_1 DMA base address bit [27:0]
R: same as in index 0h. Byte address
3h
R/W
Bits [15:0]
W: Buffer_1 DMA base count [15:0]
R: same as in index 1h. Program byte count minus one.
4h
R/W
Bits [7:0] R/W: Channel Control and Status register.
5h
R/W
Bits [19:0] Channel SamplingRate
6h
R/W
Bits [13:0] (see note below) Channel left and right volume/pan control