L9805 datasheet(20/103 Pages) STMICROELECTRONICS

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L9805

3.5 RESET

3.5.1 Introduction

There are four sources of Reset:

– NRESET pin (external source)

– Power-On Reset / Low Voltage Detection (Inter-

nal source)

– WATCHDOG (Internal Source)

– SAFEGUARD (Internal source)

The Reset Service Routine vector is located at ad-

dress FFFEh-FFFFh.

3.5.2 External Reset

The NRESET pin is both an input and an open-

drain output with integrated pull-up resistor. When

one of the internal Reset sources is active, the Re-

set pin is driven low to reset the whole application.

3.5.3 Reset Operation

The duration of the Reset condition, which is also

reflected on the output pin, is fixed at 4096 internal

CPU Clock cycles. A Reset signal originating from

an external source must have a duration of at least

1.5 internal CPU Clock cycles in order to be recog-

nised. At the end of the Power-On Reset cycle, the

MCU may be held in the Reset condition by an Ex-

ternal Reset signal. The NRESET pin may thus be

used to ensure VDD has risen to a point where the

MCU can operate correctly before the user pro-

gram is run. Following a Power-On Reset event, or

after exiting Halt mode, a 4096 CPU Clock cycle

delay period is initiated in order to allow the oscil-

lator to stabilise and to ensure that recovery has

taken place from the Reset state.

During the Reset cycle, the device Reset pin acts

as an output that is pulsed low. In its high state, an

internal pull-up resistor of about 300K

Ω is con-

nected to the Reset pin. This resistor can be pulled

low by external circuitry to reset the device.

3.5.4 Power-on Reset - Low Voltage Detection

The POR/LVD function generates a static reset

when the supply voltage is below a reference val-

ue. In this way, the Power-On Reset and Low Volt-

age Reset function are provided, in order to keep

the system in safe condition when the voltage is

too low.

The Power-Up and Power-Down thresholds are

different, in order to avoid spurious reset when the

MCU starts running and sinks current from the

supply.

The LVD reset circuitry generates a reset when

VDD is below:

– VResetON when VDD is rising

– VResetOFF when VDD is falling

The POR/LVD function is explained in Figure 9.

Power-On Reset activates the reset pull up tran-

sistor performing a complete chip reset. In the

same way a reset can be triggered by the watch-

dog, by the safeguard or by external low level at

NRESET pin. An external capacitor connected be-

tween NRESET and ground can extend the power

on reset period if required.

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