L9805 datasheet(56/103 Pages) STMICROELECTRONICS

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L9805

5.5 10-BIT A/D CONVERTER (AD10)

5.5.1 Introduction

The Analog to Digital converter is a single 10-bit

successive approximation converter with 4 input

channels. Analog voltage from external sources

are input to the converter through AD2,AD3 and

AD4 pins. Channel 1 (AD1) is connected to the in-

ternal temperature sensor (see Section 5.5.5).

Note The anti aliasing filtering must be accom-

plished using an external RC filter. The internal

AD1 channel is filtered by an RC network with ap-

prox. 1us time constant.

5.5.2 Functional Description

The result of the conversion is stored in 2 regis-

ters: the Data Register High (ADCDRH) and the

Data Register Low (ADCDRL).

The A/D converter is enabled by setting the ADST

bit in ADCCSR Register. Bits CH1 and CH0 of AD-

CCSR Register select the channel to be convert-

ed. The high and low reference voltage are con-

nected to pins VCC and AGND.

When enabled, the A/D converter performs a com-

plete conversion in 14us (with system clock

fCPU=8Mhz). The total conversion time includes

multiplex, sampling of the input voltage, 10-bit

conversion and writing DRH and DRL registers.

When the conversion is completed COCO bit

(COnversion COmpleted) is set in ADCCSR.

A conversion starts from the moment ADST bit is

set. When a conversion is running it is possible to

write the ADCCSR without stopping the ADC oper-

ations, because all the data in ADCCSR are

latched when ADST is set. This property allows to

select a different channel to be processed during

the next conversion or to manage the interrupt en-

able bit. The new setting will have effect on the

next conversion (including interrupt generation)

At the end of the conversion ADST is reset and

COCO bit is set.

Note To start a new conversion the ADST must be

set after the completion of the current one. Any

writing to ADST when a conversion is running

(COCO=0) has no effect since ADST bit is auto-

matically reset by the end of conversion event.

Figure 32. Block diagram of the Analog to Digital Converter

CH0

CH1

ADST

logic

clk

8Mhz

2 Mhz

start conversion

.....

AD0

AD9

DRH

DRL

end conversion

Vin

VCC

AGND

inputs

CSR

sampling

conversion

latch

ADIE

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