AD9879-EB datasheet(14/32 Pages) AD

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AD9879

Rev. A | Page 14 of 32

RESET AND TRANSMIT POWER-DOWN

Power-Up Sequence

On initial power-up, the RESET pin should be held low until

the power supply is stable.

Once RESET is deasserted, the AD9879 can be programmed

over the serial port. The on-chip PLL requires a maximum of

1 millisecond after the rising edge of RESET or a change of the

multiplier factor (M) to completely settle. It is recommended

that the PWRDN pin be held low during the reset and PLL

settling time. Changes to ADC Clock Select (Register 0x08) or

SYS Clock Divider N (Register 0x01) should be programmed

before the rising edge of PWRDN.

Once the PLL is frequency locked and after the PWRDN pin is

brought high, transmit data can be sent reliably.

If the PWRDN pin cannot be held low throughout the reset and

PLL settling time period, the power-down digital Tx bit or the

PWRDN pin should be pulsed after the PLL has settled. This

will ensure correct transmit filter initialization.

RESET

To initiate a hardware reset, the RESET pin should be held low

for at least 100 nanoseconds. All internally generated clocks

stop during reset. The rising edge of RESET resets the PLL clock

multiplier and reinitializes the programmable registers to their

default values. The same sequence as described in the Power-Up

Sequence section should be followed after a reset or change in M.

A software reset (writing a 1 into Bit 5 of Register 0x00) is

functionally equivalent to the hardware reset but does not force

1msMIN

5 MCLKMIN

RESET

PWRDN

Figure 5. Power-Up Sequence for Tx Data Path

Transmit Power-Down

A low level on the PWRDN pin stops all clocks linked to the

digital transmit data path and resets the CIC filter. Deasserting

PWRDN reactivates all clocks. The CIC filter is held in a reset

state for 80 MCLK cycles after the rising edge of PWRDN to

allow for flushing of the half-band filters with new input data.

Transmit data bursts should be padded with at least 20 symbols

of null data directly before the PWRDN pin is deasserted.

Immediately after the PWRDN pin is deasserted, the transmit

burst should start with a minimum of 20 null data symbols.

This avoids unintended DAC output samples caused by the

transmit path latency and filter settling time.

Software Power-Down Digital Tx (Bit 5 in Register 02x00) is

functionally equivalent to the hardware PWRDN pin and takes

effect immediately after the last register bit has been written

over the serial port.

PWRDN

TXIQ

TXSYNC

5MCLKMIN

20 NULL SYMBOLS

DATA SYMBOLS

20 NULL SYMBOLS

Figure 6. Timing Sequence to Flush Tx Data Path

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