AD9879-EB datasheet(24/32 Pages) AD

24 / 32 page

AD9879

Rev. A | Page 24 of 32

Tx SIGNAL LEVEL CONSIDERATIONS

The quadrature modulator introduces a maximum gain of 3 dB

in signal level. To visualize this, assume that both the I data and

Q data are fixed at the maximum possible digital value, x. The

output of the modulator, z is then:

z = [x cos(ωt) – x sin(ωt)]

(17)

Figure 17. 16-Quadrature Modulation

It can be shown that |z| assumes a maximum value of

()

(

gain

)

(18)

However, if the same number of bits are used to represent the |z|

values, as is used to represent the x values, an overflow occurs.

To prevent this possibility, an effective −3 dB attenuation is

internally implemented on the I and Q data path.

(

)

(

)

(19)

LOW-PASS

FILTER

AD832x

AD9879

Ω

VARIABLE GAIN

CABLE DRIVER

AMPLIFIER

CA_EN

CA_DATA

CA_CLK

DAC

Figure 18. 16-Quadrature Modulation

The following example assumes a PK/rms level of 10 dB:

Maximum Symbol Component Input Value =

(20)

±(2,047 LSBs − 0.2 dB) = ±2,000 LSBs

Maximum Complex Input RMS Value =

(21)

2,000 LSBs + 6 dB − Pk/rms (dB) = 1,265 LSBs rms

The maximum complex input rms value calculation uses both

I and Q symbol components that add a factor of 2 (6 dB) to the

formula.

Table 11 shows typical I-Q input test signals with amplitude

levels related to 12-bit full scale (FS).

Tx THROUGHPUT AND LATENCY

Data inputs impact the output fairly quickly but remain

effective due to the filter characteristics of the AD9879. Data

transmit latency through the AD9879 is easiest to describe in

terms of fSYSCLK clock cycles (4 fMCLK). The numbers quoted are

when an effect is first seen after an input value changes.

Latency of I/Q data entering the data assembler (AD9879 input)

to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles).

DC values applied to the data assembler input takes up to 176

fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle at the

DAC output.

Frequency hopping is accomplished via changing the PROFILE

input pin. The time required to switch from one frequency to

another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).

Table 11. I–Q Input Test Signals

Analog Output

Digital Input

Input Level

Modulator Output Level

Single Tone (fC – f)

I = cos(f)

FS – 0.2 dB

FS – 3.0 dB

Q = cos(f + 90°) = −sin(f)

FS – 0.2 dB

Single Tone (fC + f)

I = cos(f)

FS – 0.2 dB

FS – 3.0 dB

Q = cos(f + 270°) = +sin(f)

FS – 0.2 dB

Dual Tone (fC ± f)

I = cos(f)

FS – 0.2 dB

Q = cos(f + 180°) = −cos(f) or Q = +cos(f)

FS – 0.2 dB

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