VL6624 datasheet(92/106 Pages) STMICROELECTRONICS

92 / 106 page

Electrical characteristics

VL6624/VS6624

92/106

Table 50.

Timing specification(1)

Symbol

Parameter

Standard mode

Fast mode

Unit

Min.

Max.

Min.

Max.

fSCL

SCL clock frequency

100

400

kHz

tHD;STA

Hold time for a repeated

start

4.0

0.6

μs

tLOW

LOW period of SCL

4.7

1.3

μs

tHIGH

HIGH period of SCL

4.0

0.6

μs

tSU;STA

Set-up time for a repeated

start

4.7

0.6

μs

tHD;DAT

Data hold time (1)

300

tSU;DAT

Data Set-up time (1)

250

100

Rise time of SCL, SDA

1000

20+0.1Cb

(2)

300

Fall time of SCL, SDA

300

20+0.1Cb

(2)

300

tSU;STO

Set-up time for a

stop

4.0

0.6

μs

tBUF

Bus free time between a

stop and a

start

4.7

1.3

μs

Capacitive Load for each bus line

400

VnL

Noise Margin at the LOW level for each

connected device (including hysteresis)

0.1 VDD

VnH

Noise Margin at the HIGH level for each

connected device (including hysteresis)

0.2 VDD

All values are referred to a VIHmin = 0.9 VDD and VILmax = 0.1 VDD

Cb = capacitance of one bus line in pF

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