AD1934 datasheet(12/28 Pages) AD

12 / 28 page

AD1934

Rev. 0 | Page 12 of 28

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTERS (DACs)

The AD1934 DAC channels are arranged as single-ended, four

stereo pairs giving eight analog outputs for minimum external

components. The DACs include on-board digital reconstruction

filters with 70 dB stop-band attenuation and linear phase

response, operating at an oversampling ratio of 4 (48 kHz or

96 kHz modes) or 2 (192 kHz mode). Each channel has its own

independently programmable attenuator, adjustable in 255 steps

in increments of 0.375 dB. Digital inputs are supplied through

four serial data input pins (one for each stereo pair) and a

common frame (DLRCLK) and bit (DBCLK) clock. Alternatively,

one of the TDM modes can be used to access up to 16 channels

on a single TDM data line.

Each output pin has a nominal common-mode dc level of 1.5 V

and swings ±1.27 V for a 0 dBFS digital input signal. A single op

amp, third-order, external, low-pass filter is recommended to

remove high frequency noise present on the output pins. The

use of op amps with low slew rate or low bandwidth can cause

high frequency noise and tones to fold down into the audio

band; therefore, exercise care in selecting these components.

The voltage at CM, the common-mode reference pin, can be

used to bias the external op amps that buffer the output signals

(see the Power Supply and Voltage Reference section).

CLOCK SIGNALS

The on-chip phase locked loop (PLL) can be selected to

reference the input sample rate from either of the LRCLK pins

or 256, 384, 512, or 768 times the sample rate, referenced to the

48 kHz mode from the MCLKI pin. The default at power-up is

256 × fS from MCLKI pin. In 96 kHz mode, the master clock

frequency stays at the same absolute frequency; therefore, the

actual multiplication rate is divided by 2. In 192 kHz mode,

the actual multiplication rate is divided by 4. For example, if a

device in the AD1934 family is programmed in 256 × fS mode, the

frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.

If the AD1934 is then switched to 96 kHz operation (by writing

to the SPI or I2C port), the frequency of the master clock should

remain at 12.288 MHz, which is now 128 × fS. In 192 kHz mode,

this becomes 64 × fS.

The internal clock for the DACs varies by mode: 512 × fS (48 kHz

mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By

default, the on-board PLL generates this internal master clock

from an external clock. A direct 512 × fS (referenced to 48 kHz

mode) master clock can be used for DACs if selected in PLL

and Clock Control 1 Register.

The PLL can be powered down in PLL and Clock Control 0

or if the reference clock is unstable at power-on, power down

the PLL and then power it back up when the reference clock

has stabilized.

The internal MCLK can be disabled in PLL and Clock Control 0

The clock should be stable before it is enabled. Unless a stand-

alone mode is selected (see the Serial Control Port section), the

clock is disabled by reset and must be enabled by writing to the

SPI or I2C port for normal operation.

To maintain the highest performance possible, it is recommended

that the clock jitter of the internal master clock signal be limited

to less than 300 ps rms time interval error (TIE). Even at these

levels, extra noise or tones can appear in the DAC outputs if the

jitter spectrum contains large spectral peaks. If the internal PLL

is not being used, it is highly recommended that an independent

crystal oscillator generate the master clock. In addition, it is

especially important that the clock signal not be passed through

an FPGA, CPLD, or other large digital chip (such as a DSP)

before being applied to the AD1934. In most cases, this induces

clock jitter due to the sharing of common power and ground

connections with other unrelated digital output signals. When

the PLL is used, jitter in the reference clock is attenuated above

a certain frequency depending on the loop filter.

RESET AND POWER-DOWN

Reset sets all the control registers to their default settings.

To avoid pops, reset does not power down the analog outputs.

After reset is deasserted, and the PLL acquires lock condition,

an initialization routine runs inside the AD1934. This

initialization lasts for approximately 256 MCLKs.

The power-down bits in the PLL and Clock Control 0 and DAC

Control 1 registers power down the respective sections. All

other register settings are retained. To guarantee proper startup,

the reset pin should be pulled low by an external resistor.

AD1934 Datasheet(PDF) 12 Page - Analog Devices

AD1934 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL