AD1934 datasheet(20/28 Pages) AD

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AD1934

Rev. 0 | Page 20 of 28

CONTROL REGISTERS

DEFINITIONS

The format is the same for I2C and SPI ports. The global address for the AD1934 is 0x04, shifted left 1 bit due to the R/W bit. However, in

I2C, ADR0 and ADR1 are OR’ed into Bit 17 and Bit 8 to provide multiple chip addressing. All registers are reset to 0, except for the DAC

volume registers that are set to full volume.

Note that the first setting in each control register parameter is the default setting.

Table 14. Register Format

Global Address

R/W

Data

Bit

23:17

15:8

7:0

Table 15. Register Addresses and Functions

Address

Function

PLL and Clock Control 0

PLL and Clock Control 1

DAC Control 0

DAC Control 1

DAC Control 2

DAC individual channel mutes

DAC 1L volume control

DAC 1R volume control

DAC 2L volume control

DAC 2R volume control

DAC 3L volume control

DAC 3R volume control

DAC 4L volume control

DAC 4R volume control

Reserved

Auxiliary TDM Port Control 0

Auxiliary TDM Port Control 1

PLL AND CLOCK CONTROL REGISTERS

Table 16. PLL and Clock Control 0

Bit

Value

Function

Description

Normal operation

PLL power-down

Power-down

2:1

INPUT 256 (×44.1 kHz or 48 kHz)

MCLK pin functionality (PLL active)

INPUT 384 (×44.1 kHz or 48 kHz)

INPUT 512 (×44.1 kHz or 48 kHz)

INPUT 768 (×44.1 kHz or 48 kHz)

4:3

XTAL oscillator enabled

MCLKO pin

256 × fS VCO output

512 × fS VCO output

Off

6:5

MCLK

PLL input

DLRCLK

AUXTDMLRCLK

Reserved

Disable: DAC idle

Internal MCLK enable

Enable: DAC active

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