TMS320VC5506 datasheet(47/120 Pages) TI

47 / 120 page

Functional Overview

October 2006 − Revised January 2008

SPRS375C

Table 3−14. USB APLL Clock Mode Register Bit Functions (Continued)

BIT

NO.

FUNCTION

RESET

VALUE

BIT

NAME

PLL Voltage Controlled Oscillator (VCO) enable bit. This bit works in conjunction with MODE to enable

or disable the VCO.

MODE

VCO

OFF

X = Don’t care

MODE

PLL mode selection bit

MODE = 0

PLL operating in divide mode (VCO bypassed). When the PLL is operating in DIV mode, the

PLL Divide Factor (D) is determined by the factor K.

D = 2 if K = 1 to 15

D = 4 if K = 16

MODE = 1

PLL operating in multiply mode (VCO on). The PLL multiply and divide factors are

determined by DIV and K.

STAT

PLL lock status bit

STAT = 0

PLL operating in DIV mode (VCO bypassed)

STAT = 1

PLL operating in multiply mode (VCO on)

DIV, combined with MODE and K, defines the final PLL multiplication ratio M/D as indicated below. The USB

APLL clock frequency can be simply expressed by:

FUSB APLL CLK = FCLKIN x (M/D)

The multiplication factor M and the dividing factor D are defined in Table 3−15.

Table 3−15. M and D Values Based on MODE, DIV, and K

MODE

DIV

1 to 15

Odd

Even

K − 1

The USB clock generation and the PLL switching scheme are discussed in detail in the TMS320VC5507/5509

DSP Universal Serial Bus (USB) Module Reference Guide (literature number SPRU596) and in the Using the

USB APLL on the TMS320VC5507/5509A Application Report (literature number SPRA997).

TMS320VC5506 Datasheet(PDF) 47 Page - Texas Instruments

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