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TMS320VC5506 Datasheet(PDF) 61 Page - Texas Instruments |
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TMS320VC5506 Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 120 page  Functional Overview 61 October 2006 − Revised January 2008 SPRS375C Table 3−30. USB Module Registers (Continued) WORD ADDRESS RESET VALUE† DESCRIPTION REGISTER NAME CONTROL AND STATUS REGISTERS 0x6780 IEPCNF_0 Input Endpoint 0 Configuration xxxx xxxx 0000 0000 0x6781 IEPBCNT_0 Input Endpoint 0 Byte Count xxxx xxxx 1000 0000 0x6782 OEPCNF_0 Output Endpoint 0 Configuration xxxx xxxx 0000 0000 0x6783 OEPBCNT_0 Output Endpoint 0 Byte Count xxxx xxxx 0000 0000 0x6784 − 0x6790 Reserved 0x6791 GLOBCTL Global Control Register xxxx xxxx 0000 0000 0x6792 VECINT Vector Interrupt Register xxxx xxxx 0000 0000 0x6793 IEPINT Input Endpoint Interrupt Register xxxx xxxx 0000 0000 0x6794 OEPINT Output Endpoint Interrupt Register xxxx xxxx 0000 0000 0x6795 IDMARINT Input DMA Reload Interrupt Register xxxx xxxx 0000 0000 0x6796 ODMARINT Output DMA Reload Interrupt Register xxxx xxxx 0000 0000 0x6797 IDMAGINT Input DMA Go Interrupt Register xxxx xxxx 0000 0000 0x6798 ODMAGINT Output DMA Go Interrupt Register xxxx xxxx 0000 0000 0x6799 IDMAMSK Input DMA Interrupt Mask Register xxxx xxxx 0000 0000 0x679A ODMAMSK Output DMA Interrupt Mask Register xxxx xxxx 0000 0000 0x679B IEDBMSK Input EDB Interrupt Mask Register xxxx xxxx 0000 0000 0x679C OEDBMSK Output EDB Interrupt Mask Register xxxx xxxx 0000 0000 0x67A0 HOSTCTL Host DMA Control Register xxxx xxxx xxxx x000 0x67A1 HOSTEP Host DMA Endpoint Register xxxx xxxx x000 0000 0x67A2 HOST Host DMA Status xxxx xxxx xxxx x001 0x67F8 FNUML Frame Number Low Register xxxx xxxx 0000 0000 0x67F9 FNUMH Frame Number High xxxx xxxx xxxx x000 0x67FA PSOFTMR PreSOF Interrupt Timer Register xxxx xxxx 0000 0000 0x67FC USBCTL USB Control Register xxxx xxxx 0101 0000 0x67FD USBMSK USB Interrupt Mask Register xxxx xxxx 0000 0000 0x67FE USBSTA USB Status Register xxxx xxxx 0000 0000 0x67FF FUNADR Function Address Register xxxx xxxx x000 0000 0x7000 USBIDLECTL USB Idle Control and Status Register xxxx xxxx xxxx x000 † Hardware reset; x denotes a “don’t care.” NOTE: The USB module must be brought out of reset by setting bit 2 of the USB Idle Control and Status Register before any USB module register read or write attempt. Table 3−31. External Bus Selection Register WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE 0x6C00 EBSR[15:0] External Bus Selection Register 0000 0000 0000 0011† † The reset value is 0000 0000 0000 0001 if GPIO0 = 1 at reset; the value is 0000 0000 0000 0011 if GPIO0 = 0 at reset. |
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