TMS320VC5506 datasheet(97/120 Pages) TI

97 / 120 page

Electrical Specifications

October 2006 − Revised January 2008

SPRS375C

Table 5−24. McBSP0 Switching Characteristics†

NO.

PARAMETER

MIN

MAX

UNIT

MC1

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

MC3

tr(CKRX)

Rise time, CLKR/X

CLKR/X int

MC4

tf(CKRX)

Fall time, CLKR/X

CLKR/X int

MC11

tw(CKRXH)

Pulse duration, CLKR/X high

CLKR/X int

D−2§

D+2§

MC12

tw(CKRXL)

Pulse duration, CLKR/X low

CLKR/X int

C−2§

C+2§

MC13

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

−2

MC13

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR ext

MC14

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX int

−2

MC14

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

MC15

tdis(CKXH-DXHZ) Disable time, DX high-impedance from CLKX high following last data bit

CLKX int

MC15

tdis(CKXH-DXHZ) Disable time, DX high-impedance from CLKX high following last data bit

CLKX ext

Delay time, CLKX high to DX valid.

CLKX int

Delay time, CLKX high to DX valid.

This applies to all bits except the first bit transmitted.

CLKX ext

MC16

td(CKXH-DXV)

Delay time, CLKX high to DX valid¶

DXENA = 0

CLKX int

MC16

td(CKXH-DXV)

Delay time, CLKX high to DX valid

DXENA = 0

CLKX ext

Only applies to first bit transmitted when in Data Delay

DXENA = 1

CLKX int

2P + 1

Only applies to first bit transmitted when in Data Delay

1 or 2 (XDATDLY = 01b or 10b) modes

DXENA = 1

CLKX ext

2P + 4

Enable time, DX driven from CLKX high¶

DXENA = 0

CLKX int

−1

MC17

ten(CKXH-DX)

Enable time, DX driven from CLKX high

DXENA = 0

CLKX ext

MC17

ten(CKXH-DX)

Only applies to first bit transmitted when in Data Delay

DXENA = 1

CLKX int

P − 1

Only applies to first bit transmitted when in Data Delay

1 or 2 (XDATDLY= 01b or 10b) modes

DXENA = 1

CLKX ext

P + 6

Delay time, FSX high to DX valid¶

DXENA = 0

FSX int

MC18

td(FXH-DXV)

Delay time, FSX high to DX valid

DXENA = 0

FSX ext

MC18

td(FXH-DXV)

Only applies to first bit transmitted when in Data Delay

DXENA = 1

FSX int

2P + 1

Only applies to first bit transmitted when in Data Delay

0 (XDATDLY= 00b) mode.

DXENA = 1

FSX ext

2P + 10

Enable time, DX driven from FSX high¶

DXENA = 0

FSX int

MC19

ten(FXH-DX)

Enable time, DX driven from FSX high

DXENA = 0

FSX ext

MC19

ten(FXH-DX)

Only applies to first bit transmitted when in Data Delay

DXENA = 1

FSX int

P − 3

Only applies to first bit transmitted when in Data Delay

0 (XDATDLY= 00b) mode

DXENA = 1

FSX ext

P + 8

† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are

also inverted.

‡ P = 1/CPU clock frequency. For example, when running parts at 108 MHz, use P = 9.26 ns.

§ T=CLKRX period = (1 + CLKGDV) * P

C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

¶ See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA)

and data delay features of the McBSP.

TMS320VC5506 Datasheet(PDF) 97 Page - Texas Instruments

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